United States Department of Commerce (DOC)

Submit ticket request  // Limit: 4* // Tickets Available: 4

*Each applicant may submit a maximum of one SRFA 1 application and three SRFA 2 applications.

This NOFO is the second in a series that NTIA will issue and administer under the Public Wireless Supply Chain Innovation Fund (Innovation Fund). This NOFO is divided into two topic areas: open radio unit (RU) commercialization and open RU innovation. Throughout this document, open RU commercialization is referred to as “specific research focus area 1” (SRFA 1) and open RU innovation is referred to as “specific research focus area 2” (SRFA 2). A brief description of each SRFA is below:
 

• SRFA 1: Accelerating the development of open RU products to the point where they meet carrier needs and are ready for commercial trials; and
• SRFA 2: Improving the overall performance and capabilities of open RUs through targeted research and development.

Applications in response to this NOFO must address either SRFA 1 or SRFA 2. A single application cannot address both SRFAs. If an application is submitted addressing both SRFAs, it will be rejected. Applicants interested in applying for both SRFAs must submit a separate application for each SRFA. Applicants may only include one project per application, regardless of SRFA. Individual submissions containing multiple proposed projects will be rejected. Each applicant may submit a maximum of one SRFA 1 application and three SRFA 2 applications. Each SRFA 2 application must address at least one, and may address more than one, topic area listed in Section 3.3.1.

NTIA will award up to $420,000,000 under this NOFO. The amount of funding NTIA expects to award per project differs by SRFA, as follows:
• SRFA 1: NTIA expects to award $25,000,000-$45,000,000 per project.
• SRFA 2: NTIA expects to award $5,000,000-$10,000,000 per project.

Institutionally Coordinated // Limit: 1 // L. Folks (Semiconductor Strategy)

Please contact the Center for Semiconductor Manufacturing (CSM)  for more information. 

Eligible applicants can only submit one concept plan paper under this NOFO.

Program Priorities

“Advanced packaging” refers to many chips with diverse functions assembled tightly together on a substrate in two or three dimensions at extremely fine dimensions. This method achieves function, performance, and power savings far greater than can be achieved with conventionally packaged chips on a printed circuit board. Recent advances in artificial intelligence, for example, would not be possible without advanced packaging.

Advanced packaging can be a transformative capability that helps U.S. manufacturers compete globally, but there are many technological challenges to solve. The CHIPS Research and Development Office has established the CHIPS National Advanced Packaging Manufacturing Program to address these challenges, including:

• How do we design and assemble chips so tightly that they behave like a single traditional large chip, but with the production efficiency and cost savings of advanced packaging?

• How do we supply power to and dissipate heat from such tightly coupled assemblies?

• How do we test and repair such complex assemblies?

• How do we ensure their reliability since traditional methods of visual inspection cannot be performed on such small, tightly packaged dimensions?

The CHIPS NAPMP will enable the development of a robust domestic advanced packaging ecosystem by:

• Establishing an advanced packaging piloting facility (or facilities) that accelerates the transfer of innovations in packaging, equipment, and process development into manufacturing;

• Driving the development of digital tools to reduce the time and cost of advanced packaging engineering; and,

• Establishing and supporting partnerships among industry, academia and training entities, and government to contribute to an advanced packaging workforce.

The six priority research investment areas of the CHIPS NAPMP are:

• Materials and substrates

• Equipment, tools, and processes

• Power delivery and thermal management for advanced packaging assemblies

• Photonics and connectors that communicate with the outside world

• A chiplet ecosystem

• Co-design of multi-chiplet systems with automated tools